As advances in integrated circuit technology are achieved, device geometries are shrinking in size and the operating voltages (Vdd) are decreasing. Integrated circuit designers must account for on-chip transient noise when developing integrated circuits, because the lower the operating voltage, the more likely a voltage drop due to an instantaneous current draw event (i.e., a noise event) becomes unacceptable because the functional logic blocks on the integrated circuit may not function reliably. For example, as each of several functional logic blocks is powered up and used, more and more current is drawn and more and more transient noise events occur. There are several contributing factors to the increased need to design more transient-noise-tolerant circuitry, including: (1) the inherent performance increase per technology node is shrinking, therefore there is less performance to offer; (2) the performance drop-off vs. voltage curve is getting steeper with thinner oxides and lower Vdds; (3) the increased overall on-chip density may lead to higher current per unit area, which in turn leads to more noise; and (4) higher operating frequencies limit the capability to satisfy instantaneous current demands from off-chip, which leads to larger magnitude on-chip noise pulses.
Generally, events that create worst-case on-chip transient noise (i.e., high instantaneous current demand or dI/dt, which is the time rate of change of current) occur infrequently. However, the worst case noise scenario must be taken into account during the integrated circuit design process. Typically, a “noise budget” is set, and all facets of the integrated circuit design must take this budget into account, with the goal being to minimize the noise budget. In particular, passive noise limitation techniques exist that typically involve a trade-off of performance or power. In one example, the at-circuit minimum voltage may be reduced when closing timing, which results in reduced performance. In another example, two paths in a timing test may be skewed farther apart, which likewise results in reduced performance. In yet another example, the power supply may be increased in order to keep the at-circuit voltage stable, which undesirably results in higher power consumption. In a further example, decoupling capacitors can be added to the integrated circuit in order to limit supply rail collapse due to transient noise events. This, however, consumes area and power.
Consequently, there is a need to guard band against the above-mentioned problems in order to ensure that multiple logic blocks, which can have simultaneous high current demand events, will function reliably while at the same time maintain optimal performance and optimal power consumption. For these reasons, a need exists for system architectures for and methods of scheduling on-chip and across-chip active noise events in an integrated circuit, in order to avoid simultaneous active transient noise events.